1. Field of the Invention
The invention relates to an integrated digital circuit arrangement with MOS field-effect transistors, which arrangement comprises a combinatorial circuit for applying a logic operation to a plurality of input signals, which combinatorial circuit comprises a plurality of "branches" arranged as NAND-NAND logic gates, there being provided means for applying said input signals as well as an output, which is coupled to a first node of the arrangement, whose potential at a specific instant is representative of the result of the logic operation and depends on whether the capacitance of the first node is charged or not.
2. Description of the Prior Art
Such a circuit arrangement is known and is employed in the integrated Philips circuits SAB 3022B, SAB 3032D. These devices employ an N-MOS circuit in dynamic two-phase technique, which operates as follows:
A buffer circuit, which is clocked by non-overlapping clock signals, transfers the logic information from a node of the combinatorial circuit to an output with a delay of one clock period. For a reliable transfer of information it is important that this node is already at a precharge potential when it receives said information. In other words, the node should be precharged at the instant that the information arrives there. If a logic "1" is to be transferred via the node, this node is isolated after being pre-charged until the potential (which in this case remains high) is sampled for further information transfer. If a logic "0" is to be transferred the node is discharged to a low potential via one or more branches of the combinatorial circuit, after which this potential is sampled.
It is found that when such a circuit arrangement is used the frequency of the clock signals is limited because pre-charging and especially discharging of the node takes too much time. This is because numerous branches of the combinatorial circuit are connected to the node, so that the capacitance of this node is substantial, while for example under specific circumstances discharging via only one branch should be possible. It should be borne in mind that one such branch when conducting still represents a significant resistance, which has an adverse effect on the discharge time. Said resistance can only be reduced by use of larger transistors, which is not desirable in view of the required substrate area.